According to Wccftech, an ASUS representative in China, General Manager Tony, accidentally revealed AMD’s upcoming flagship processor, the Ryzen 9 9950X3D2, during a review of the Ryzen 7 9850X3D. The leak occurred when a folder named “9950X3DV2” was visible on his test system, as spotted by leaker @9550pro. The chip is confirmed to be a 16-core, 32-thread processor that adds a second 3D V-Cache chiplet, giving it a massive 192MB of total L3 cache, up from 128MB on the standard 9950X3D. It’s expected to boost up to 5.6 GHz, have a 200W TDP, and retain RDNA 2-based integrated graphics. While AMD hasn’t set a launch date, this slip suggests the processor is already in the hands of key partners and could launch soon.
The Double Cache Gamble
Here’s the thing about AMD’s X3D strategy: it’s been a one-CCD game for the high-core-count parts. The 7950X3D and 9950X3D had cache on only one of their two core chiplets (CCDs). This was a clever hack for gaming, where most titles don’t scale beyond 8 cores anyway. You’d let the cached CCD handle the game threads and the faster, non-cached CCD handle everything else.
But the “X3D2” changes that completely. It’s putting a 64MB 3D V-Cache stack on both CCDs. That’s 192MB of L3 cache sitting on the CPU. For workloads that love cache—and that’s not just games, but also certain simulation, compilation, and database tasks—this could be a monster. The trade-off? Thermals and clocks. The report notes a 30W higher TDP (200W) and a 100 MHz lower boost clock. Piling more cache on top of the cores makes it harder to keep them cool and run them fast. So, AMD is betting that sheer cache volume will outweigh those slight frequency penalties.
Why The “V2” Name?
Now, the folder name “9950X3DV2” is interesting. Is that the final product name? Maybe. “X3D2” is a bit of a mouthful, and “V2” could simply denote this second-generation, dual-cache design. It signals a more substantial architectural shift than just a new model number. This isn’t just a refresh; it’s a new configuration of the silicon. I think the bigger question is: how does the system manage this cache? With two cached CCDs, the old driver-based thread director from the first dual-CCD X3D chips might not be as critical. Basically, you can throw threads anywhere and they’ll have a huge pool of cache. That’s a simpler, more elegant solution if it works.
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Waiting For Real Game Benchmarks
So we’ve seen a Geekbench run or two where it beats the standard 9950X3D in multi-threaded tests. Big deal. That’s almost a given with more cache on both CCDs. What everyone wants to know is: what does this do for gaming? The first-gen dual-CCD X3D chips were gaming champions, but they required software tuning to park threads on the “right” CCD.
Will the 9950X3D2 just brute-force its way to higher frames without that fuss? Or will there be new scheduling quirks? The potential is huge—imagine a chip that’s not just the best for gaming, but also dominates in heavily-threaded production work. That’s the holy grail. But until we see independent reviews with a suite of games, it’s all just speculation fueled by a leaked folder name. AMD’s got our attention. Now we need the benchmarks.
